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1 LTC1546 applicatio s u features typical applicatio n u descriptio u , ltc and lt are registered trademarks of linear technology corporation. complete dte or dce multiprotocol serial interface with db-25 connector n data networking n csu and dsu n data routers n software-selectable transceiver supports: rs232, rs449, eia530, eia530-a, v.35, v.36, x.21 n tuv telecom services inc. certified net1, net2 and tbr2 compliant n on-chip cable termination n pin compatible with ltc1543 n complete dte or dce port with ltc1544 n operates from single 5v supply n small footprint the ltc ? 1546 is a 3-driver/3-receiver multiprotocol trans- ceiver with on-chip cable termination. when combined with the ltc1544, this chip set forms a complete software- selectable dte or dce interface port that supports the rs232, rs449, eia530, eia530-a, v.35, v.36 and x.21 protocols. all necessary cable termination is provided inside the LTC1546. in most applications, the LTC1546 replaces both an ltc1543 and an ltc1344a without any changes to the pc board. the LTC1546 runs from a single 5v supply using an internal charge pump that requires only five space-saving surface mounted capacitors. the LTC1546 is available in a 28-lead ssop surface mount package. software-selectable multiprotocol transceiver with termination d2 d1 ltc1544 rts dtr dsr dcd cts d3 r2 r1 r4 r3 LTC1546 ll txd scte txc rxc rxd 2 14 24 11 15 12 17 9 3 1 4 19 20 623 22 5 13 8 10 18 7 16 1546 ta01 d1 scte b scte a (113) txd b txd a (103) rxc a (115) rxc b rxd a (104) rxd b rts a (105) rts b dtr a (108) dtr b cts a (106) cts b ll a (141) sg (102) shield (101) db-25 connector txc a (114) dcd a (107) dcd b dsr a (109) dsr b d4 d2 d3 r1 r2 r3 txc b t t t t t
2 LTC1546 order part number (note 1) supply voltage ....................................................... 6.5v input voltage transmitters ........................... C 0.3v to (v cc + 0.3v) receivers ............................................... C 18v to 18v logic pins .............................. C 0.3v to (v cc + 0.3v) output voltage transmitters ................. (v ee C 0.3v) to (v dd + 0.3v) receivers ................................ C 0.3v to (v cc + 0.3v) v ee ........................................................ C 10v to 0.3v v dd ....................................................... C 0.3v to 10v short-circuit duration transmitter output ..................................... indefinite receiver output .......................................... indefinite v ee .................................................................. 30 sec operating temperature range LTC1546c ............................................... 0 c to 70 c LTC1546i ........................................... C 40 c to 85 c storage temperature range ................ C 65 c to 150 c lead temperature (soldering, 10 sec)................. 300 c LTC1546cg LTC1546ig consult factory for parts specified with wider operating temperature ranges. t jmax = 150 c, q ja = 90 c/ w* 1 2 3 4 5 6 7 8 9 10 11 12 13 14 top view 28 27 26 25 24 23 22 21 20 19 18 17 16 15 c1 c1 + v dd v cc d1 d2 d3 r1 r2 r3 m0 m1 m2 dce/dte c2 + c2 v ee gnd d1 a d1 b d2 a d2 b d3/r1 a d3/r1 b r2 a r2 b r3 a r3 b r3 charge pump r1 d2 d1 r2 d3 g package 28-lead plastic ssop t t t t t the l denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v cc = 5v (notes 2, 3) symbol parameter conditions min typ max units supplies i cc v cc supply current (dce mode, rs530, rs530-a, x.21 modes, no load 14 ma all digital pins = gnd or v cc ) rs530, rs530-a, x.21 modes, full load l 100 130 ma v.35 mode l 126 170 ma v.28 mode, no load 20 ma v.28 mode, full load l 35 75 ma no-cable mode l 60 500 m a p d internal power dissipation (dce mode) rs530, rs530-a, x.21 modes, full load 410 mw v.35 mode, full load 625 mw v.28 mode, full load 150 mw v + positive charge pump output voltage v.11 or v.28 mode, no load l 8.0 9.3 v v.35 mode l 7.0 8.0 v v.28 mode, with load l 8.0 8.7 v v.28 mode, with load, i dd = 10ma 6.5 v v C negative charge pump output voltage v.28 mode, no load C 9.6 v v.28 mode, full load l C 7.5 C 8.5 v v.35 mode l C 5.5 C 6.5 v rs530, rs530-a, x.21 modes, full load l C 4.5 C 6.0 v * q ja soldered to a circuit board is typically 60 c/w absolute axi u rati gs w ww u package/order i for atio uu w electrical characteristics
3 LTC1546 the l denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v cc = 5v (notes 2, 3) symbol parameter conditions min typ max units f osc charge pump oscillator frequency 500 khz t r charge pump rise time no-cable mode/power-off to normal operation 2 ms logic inputs and outputs v ih logic input high voltage l 2v v il logic input low voltage l 0.8 v i in logic input current d1, d2, d3 l 10 m a m0, m1, m2, dce = gnd l C 120 C 75 C 30 m a m0, m1, m2, dce = v cc l 10 m a v oh output high voltage i o = C 3ma l 3 4.5 v v ol output low voltage i o = 3ma l 0.3 0.45 v i osr output short-circuit current 0v v o v cc l C50 50 ma i ozr three-state output current m0 = m1 = m2 = v cc , 0v v o v cc 1 m a v.11 driver v odo open circuit differential output voltage r l = 1.95k (figure 1) l 5v v odl loaded differential output voltage r l = 50 w (figure 1) 0.5v odo 0.67v odo v r l = 50 w (figure 1) l 2v d v od change in magnitude of differential r l = 50 w (figure 1) l 0.2 v output voltage v oc common mode output voltage r l = 50 w (figure 1) l 3v d v oc change in magnitude of common mode r l = 50 w (figure 1) l 0.2 v output voltage i ss short-circuit current v out = gnd 150 ma i oz output leakage current ? v a ? and ? v b ? 0.25v, power off or l 1 100 m a no-cable mode or driver disabled t r , t f rise or fall time (figures 2, 13) l 21525 ns t plh input to output rising (figures 2, 13) l 15 40 65 ns t phl input to output falling (figures 2, 13) l 15 40 65 ns d t input to output difference, ? t plh C t phl ? (figures 2, 13) l 0312 ns t skew output to output skew (figures 2, 13) 3 ns v.11 receiver v th input threshold voltage C 7v v cm 7v l C 0.2 0.2 v d v th input hysteresis C 7v v cm 7v l 15 40 mv r in input impedance C7v v cm 7v (figure 3) l 100 103 w t r , t f rise or fall time c l = 50pf (figures 4, 14) 15 ns t plh input to output rising c l = 50pf (figures 4, 14) l 50 90 ns t phl input to output falling c l = 50pf (figures 4, 14) l 50 90 ns d t input to output difference, ? t plh C t phl ? c l = 50pf (figures 4, 14) l 0425 ns v.35 driver v od differential output voltage open circuit, r l = 1.95k (figure 5) l 1.2 v with load, C 4v v cm 4v (figure 6) 0.44 0.55 0.66 v v oa , v ob single-ended output voltage open circuit, r l = 1.95k (figure 5) l 1.2 v v oc transmitter output offset r l = 50 w (figure 5) l 0.6 v electrical characteristics
4 LTC1546 the l denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v cc = 5v (notes 2, 3) symbol parameter conditions min typ max units i oh transmitter output high current v a , v b = 0v l C 13 C 11 C 9.0 ma i ol transmitter output low current v a , v b = 0v l 9.0 11 13 ma i oz transmitter output leakage current ? v a ? and ? v b ? 0.25v l 1 100 m a r od transmitter differential mode impedance l 50 100 150 w r oc transmitter common mode impedance C 2v v cm 2v (figure 7) 135 150 165 w t r , t f rise or fall time (figures 8, 13) 5 ns t plh input to output (figures 8, 13) l 15 35 65 ns t phl input to output (figures 8, 13) l 15 35 65 ns d t input to output difference, ? t plh C t phl ? (figures 8, 13) l 016 ns t skew output to output skew (figures 8, 13) 4 ns v.35 receiver v th differential receiver input threshold voltage C 2v v cm 2v (figure 9) l C 0.2 0.2 v d v th receiver input hysteresis C 2v v cm 2v (figure 9) l 15 40 mv r id receiver differential mode impedance C 2v v cm 2v l 90 103 110 w r ic receiver common mode impedance C 2v v cm 2v (figure 10) 135 150 165 w t r , t f rise or fall time c l = 50pf (figures 4, 14) 15 ns t plh input to output c l = 50pf (figures 4, 14) l 50 90 ns t phl input to output c l = 50pf (figures 4, 14) l 50 90 ns d t input to output difference, ? t plh C t phl ? c l = 50pf (figures 4, 14) l 0425 ns v.28 driver v o output voltage open circuit l 10 v r l = 3k (figure 11) l 5 8.5 v i ss short-circuit current v out = gnd l 150 ma r oz power-off resistance C 2v < v o < 2v, power off l 300 w or no-cable mode sr slew rate r l = 7k, c l = 0 (figures 11, 15) l 430v/ m s t plh input to output r l = 3k, c l = 2500pf (figures 11, 15) l 1.5 2.5 m s t phl input to output r l = 3k, c l = 2500pf (figures 11, 15) l 1.5 2.5 m s v.28 receive r v thl input low threshold voltage (figure 12) l 1.2 0.8 v v tlh input high threshold voltage (figure 12) l 2 1.2 v d v th receiver input hysteresis (figure 12) l 0 0.05 0.3 v r in receiver input impedance C 15v v a 15v l 357 k w t r , t f rise or fall time c l = 50pf (figures 12, 16) 15 ns t plh input to output c l = 50pf (figures 12, 16) l 60 300 ns t phl input to output c l = 50pf (figures 12, 16) l 160 300 ns note 1: absolute maximum ratings are those values beyond which the life of the device may be impaired. note 2: all currents into device pins are positive; all currents out of device are negative. all voltages are referenced to device ground unless otherwise specified. note 3: all typicals are given for v cc = 5v, c1 = c2 = c vcc = c vdd = 1 m f, c vee = 3.3 m f and t a = 25 c. electrical characteristics
5 LTC1546 typical perfor a ce characteristics uw data rate (kbd) 10 supply current (ma) 1000 180 170 160 150 140 130 120 110 100 90 1546 ?g01 100 10000 data rate (kbd) 10 supply current (ma) 1000 150 145 140 135 130 1546 ?g02 100 10000 data rate (kbd) 10 supply current (ma) 50 35 34 33 32 31 30 1546 ?g03 20 100 temperature ( c) ?0 i cc (ma) 115 110 105 100 95 90 85 20 60 1546 ?g04 ?0 0 40 80 100 temperature ( c) ?0 i cc (ma) 140 135 130 125 20 60 1546 ?g05 ?0 0 40 80 100 temperature ( c) ?0 i cc (ma) 40 38 36 34 32 30 20 60 1546 ?g06 ?0 0 40 80 100 v.11 mode supply current vs data rate v.35 mode supply current vs data rate v.28 mode supply current vs data rate v.11 mode i cc vs temperature v.35 mode i cc vs temperature v.28 mode i cc vs temperature c1 C (pin 1): capacitor c1 negative terminal. connect a 1 m f capacitor between c1 + and c1 C . c1 + (pin 2): capacitor c1 positive terminal. connect a 1 m f capacitor between c1 + and c1 C . v dd (pin 3): generated positive supply voltage for v.28. connect a 1 m f capacitor to ground. v cc (pin 4): positive supply voltage input. 4.75v v cc 5.25v. bypass with a 1 m f capacitor to ground. d1 (pin 5): ttl level driver 1 input. d2 (pin 6): ttl level driver 2 input. d3 (pin 7): ttl level driver 3 input. uu u pi fu ctio s r1 (pin 8): cmos level receiver 1 output. r2 (pin 9): cmos level receiver 2 output. r3 (pin 10): cmos level receiver 3 output. m0 (pin 11): ttl level mode select input 0 with pull-up to v cc . see table 1. m1 (pin 12): ttl level mode select input 1 with pull-up to v cc . see table 1. m2 (pin 13): ttl level mode select input 2 with pull-up to v cc . see table 1. dce/dte (pin 14): ttl level mode select input with pull- up to v cc . see table 1.
6 LTC1546 block diagra w uu u pi fu ctio s r3 b (pin 15): receiver 3 noninverting input. r3 a (pin 16): receiver 3 inverting input. r2 b (pin 17): receiver 2 noninverting input. r2 a (pin 18): receiver 2 inverting input. d3/r1 b (pin 19): receiver 1 noninverting input and driver 3 noninverting output. d3/r1 a (pin 20): receiver 1 inverting input and driver 3 inverting output. d2 b (pin 21): driver 2 noninverting output. d2 a (pin 22): driver 2 inverting output. d1 b (pin 23): driver 1 noninverting output. d1 a (pin 24): driver 1 inverting output. gnd (pin 25): ground. v ee (pin 26): negative supply voltage. connect a 3.3 m f capacitor to gnd. c2 C (pin 27): capacitor c2 negative terminal. connect a 1 m f capacitor between c2 + and c2 C . c2 + (pin 28): capacitor c2 positive terminal. connect a 1 m f capacitor between c2 + and c2 C . c1 c1 + v dd v cc c1 c1 + v dd v cc c2 + c2 v ee gnd c2 + c2 v ee gnd charge pump d1 d1a 50 125 50 s1 s2 d1b d1 d2 d2a 50 125 50 s1 s2 d2b s3 s2 20k 20k 20k 20k 125 s2 s3 125 10k 6k s1 51.5 d3/r1 a d3/r1 b 51.5 10k 10k 10k 51.5 r2a r2b 51.5 d2 d3 dce/dte r1 d3 r1 r2 r2 6k 20k 20k s2 s3 125 10k 10k 51.5 r3a r3b 1546 bd 51.5 r3 r3 6k 28 1 2 3 4 5 6 7 14 8 9 10 27 26 25 24 23 22 21 20 19 18 17 16 15
7 LTC1546 figure 1. v.11 driver dc test circuit figure 2. v.11 driver ac test circuit figure 4. v.11, v.35 receiver ac test circuit figure 3. input impedance test circuit 1546 f01 v od v oc r l r l a b d a b d 1546 f02 r l 100 w c l 100pf c l 100pf r 1546 f03 v cm = 7v b i b a + i a 2(v b ?v a ) i b ?i a r in = a b 1546 f04 r c l figure 5. v.35 driver open-circuit test 1546 f05 v od v oc r l 50 v ob v oa 125 50 r l 1546 f06 50 v ob v oa 125 125 50 50 50 v cm figure 6. v.35 driver test circuit 1546 f07 50 125 50 v cm = 2v + 1546 f08 50 50 125 125 50 50 1546 f09 v th v cm + + r figure 7. v.35 driver common mode impedance test circuit figure 8. v.35 driver ac test circuit figure 9. v.35 receiver dc test circuit 1546 f10 51.5 125 51.5 v cm = 2v + figure 10. receiver common mode impedance test circuit a d 1546 f11 r l c l r a 1546 f12 c l v a figure 11. v.28 driver test circuit figure 12. v.28 receiver test circuit test circuits
8 LTC1546 switchi g ti e wavefor s uw w figure 14. v.11, v.35 receiver propagation delays figure 13. v.11, v.35 driver propagation delays v od2 ? od2 0v 1.5v 0v 1.5v t plh v oh v ol b ?a r t phl 1546 f14 f = 1mhz : t r 10ns : t f 10ns input output 5v 1.5v 1.5v 50% 10% 90% t plh t r 0v v o v o ? o d b ?a a b t phl t skew t skew 1546 f13 1/2 v o f = 1mhz : t r 10ns : t f 10ns 50% 10% 90% t f ode selectio w u LTC1546 mode name m2 m1 m0 dce/dte d1 d2 d3 r1 r2 r3 not used (default v.11) 0000 v.11 v.11 z v.11 v.11 v.11 rs530a 0010 v.11 v.11 z v.11 v.11 v.11 rs530 0100 v.11 v.11 z v.11 v.11 v.11 x.21 0110 v.11 v.11 z v.11 v.11 v.11 v.35 1000 v.35 v.35 z v.35 v.35 v.35 rs449/v.36 1010 v.11 v.11 z v.11 v.11 v.11 v.28/rs232 1100 v.28 v.28 z v.28 v.28 v.28 no cable 1110zzzzzz not used (default v.11) 0001 v.11 v.11 v.11 z v.11 v.11 rs530a 0011 v.11 v.11 v.11 z v.11 v.11 rs530 0101 v.11 v.11 v.11 z v.11 v.11 x.21 0111 v.11 v.11 v.11 z v.11 v.11 v.35 1001 v.35 v.35 v.35 z v.35 v.35 rs449/v.36 1011 v.11 v.11 v.11 z v.11 v.11 v.28/rs232 1101 v.28 v.28 v.28 z v.28 v.28 no cable 1111zzzzzz table 1
9 LTC1546 figure 15. v.28 driver propagation delays figure 16. v.28 receiver propagation delays v ih v il 1.3v 0.8v 1.7v 2.4v t phl v oh v ol a r t plh 1546 f16 3v 0v 1.5v 0v ?v 3v 1.5v 0v 3v ?v t phl t f v o ? o d a t plh t r 1546 f15 sr = 6v t f sr = 6v t r switchi g ti e wavefor s uw w overview the LTC1546 and ltc1544 form a complete software- selectable dte or dce interface port that supports the rs232, rs449, eia530, eia530-a, v.35, v.36 and x.21 protocols. cable termination is provided on-chip, elimi- nating the need for discrete termination designs. a complete dce-to-dte interface operating in eia530 mode is shown in figure 17. the LTC1546 half of each port is used to generate and appropriately terminate the clock and data signals. the ltc1544 is used to generate the control signals along with ll (local loopback). mode selection the interface protocol is selected using the mode select pins m0, m1 and m2 (see table 1). for example, if the port is configured as a v.35 interface, the mode selection pins should be m2 = 1, m1 = 0, m0 = 0. for the control signals, the drivers and receivers will operate in v.28 (rs232) electrical mode. for the clock and data signals, the drivers and receivers will operate in v.35 electrical mode. the dce/dte pin will configure the port for dce mode when high, and dte when low. the interface protocol may be selected simply by plugging the appropriate interface cable into the connector. the mode pins are routed to the connector and are left uncon- nected (1) or wired to ground (0) in the cable as shown in figure 18. the internal pull-up current sources will ensure a binary 1 when a pin is left unconnected. the mode selection may also be accomplished by using jumpers to connect the mode pins to ground or v cc . when the cable is removed, leaving all mode pins uncon- nected, the LTC1546/ltc1544 will enter no-cable mode. in this mode the LTC1546/ltc1544 supply current drops to less than 500 m a and the LTC1546/ltc1544 driver outputs are forced into a high impedance state. at the same time, the r2 and r3 receivers of the LTC1546 are differentially terminated with 103 w and the other receiv- ers on the LTC1546 and ltc1544 are terminated with 30k w to ground. applicatio s i for atio wu uu
10 LTC1546 figure 17. complete multiprotocol interface in eia530 mode LTC1546 dce dte LTC1546 1546 f17 d3 r1 103 w 103 w 103 w r3 ltc1544 d3 d4 r4 d2 r1 r4 r2 r3 ll txc rxc rxd txd scte txc rxc rxd serial controller d2 103 w scte r2 d1 103 w txd r3 r1 d2 d1 ltc1544 d3 r2 r1 d1 r3 d2 d1 d4 txd scte txc rxc rxd rts dtr dcd dsr cts ll rts dtr dcd dsr cts rts dtr dcd dsr cts ll serial controller r2 d3 cable termination traditional implementations used expensive relays to switch resistors or required the user to change termina- tion modules every time a new interface standard was selected. switching the terminations with fets is difficult because the fets must remain off when the signal voltage is beyond the supply voltage. alternatively, custom cables may contain termination in the cable head or route signals to various terminations on the board. the LTC1546/ltc1544 chipset solves the cable termina- tion switching problem by automatically providing the appropriate termination and switching on-chip for the v.10 (rs423), v.11 (rs422), v.28 (rs232) and v.35 electrical protocols. applicatio s i for atio wu uu
11 LTC1546 v.10 (rs423) interface all v.10 drivers and receivers necessary for the rs449, eia530, eia530-a, v.36 and x.21 protocols are imple- mented on the ltc1544. a typical v.10 unbalanced interface is shown in figure 19. a v.10 single-ended generator with output a and ground c is connected to a differential receiver with input a ' con- nected to a, and ground c ' connected via the signal return to ground c. usually, no cable termination is required for v.10 interfaces, but the receiver inputs must be compliant with the impedance curve shown in figure 20. the v.10 receiver configuration in the ltc1544 is shown in figure 21. in v.10 mode, switch s3 inside the ltc1544 is turned off. the noninverting input is disconnected inside the ltc1544 receiver and connected to ground. the cable termination is then the 30k input impedance to ground of the ltc1544 v.10 receiver. v.11 (rs422) interface a typical v.11 balanced interface is shown in figure 22. a v.11 differential generator with outputs a and b and ground c is connected to a differential receiver with input a ' connected to a, input b ' connected to b, and ground c ' connected via the signal return to ground c. the v.11 figure 18: single port dce v.35 mode selection in the cable nc nc cable 1546 f18 11 12 13 14 LTC1546 ltc1544 connector 14 13 12 11 (data) m0 m1 m2 dce/dte dce/dte m2 m1 m0 (data) figure 20. v.10 receiver input impedance figure 19. typical v.10 interface aa ' cc ' generator balanced interconnecting cable load cable termination receiver 1546 f19 i z v z 10v ?.25ma 3.25ma ?v 3v 10v 1546 f20 applicatio s i for atio wu uu
12 LTC1546 interface has a differential termination at the receiver end that has a minimum value of 100 w . the termination resistor is optional in the v.11 specification, but for the high speed clock and data lines, the termination is essen- tial to prevent reflections from corrupting the data. the receiver inputs must also be compliant with the imped- ance curve shown in figure 20. in v.11 mode, all switches are off except s1 of the LTC1546s receivers which connects a 103 w differential termination impedance to the cable as shown in figure 23 1 . the ltc1544 only handles control signals, so no termination other than its v.11 receivers 30k input imped- ance is necessary. v.28 (rs232) interface a typical v.28 unbalanced interface is shown in figure 24. a v.28 single-ended generator with output a and ground c is connected to a single-ended receiver with input a ' figure 22. typical v.11 interface figure 21. v.10 receiver configuration r5 20k ltc1544 receiver 1546 f21 a b a ' b ' c ' r8 6k s3 r6 10k r7 10k gnd r4 20k aa ' b c b ' c ' generator balanced interconnecting cable load cable termination receiver 100 w min 1546 f22 figure 24. typical v.28 interface figure 25. v.28 receiver configuration figure 23. v.11 receiver configuration r3 124 w r5 20k LTC1546 receiver 1546 f23 a ' b ' c ' r1 51.5 w r8 6k s2 s3 r2 51.5 w r6 10k r7 10k gnd r4 20k s1 connected to a and ground c ' connected via the signal return to ground c. in v.28 mode, s3 is closed inside the LTC1546/ltc1544 which connects a 6k (r8) impedance to ground in parallel with 20k (r5) plus 10k (r6) for a combined impedance of 5k as shown in figure 25. proper termination is only pro- vided when the b input of the receivers is floating, since s1 of the LTC1546s r2 and r3 receivers remains on in v.28 mode 1 . the noninverting input is disconnected inside the LTC1546/ltc1544 receiver and connected to a ttl level reference voltage to give a 1.4v receiver trip point. aa ' cc ' generator balanced interconnecting cable load cable termination receiver 1546 f24 r3 124 w r5 20k LTC1546 receiver 1546 f25 a ' b ' c ' r1 51.5 w r8 6k s2 s3 r2 51.5 w r6 10k r7 10k gnd r4 20k s1 1 actually, there is no switch s1 in receivers r2 and r3. however, for simplicity, all termination networks on the LTC1546 can be treated identically if it is assumed that an s1 switch exists and is always closed on the r2 and r3 receivers. applicatio s i for atio wu uu
13 LTC1546 v.35 interface a typical v.35 balanced interface is shown in figure 26. a v.35 differential generator with outputs a and b and ground c is connected to a differential receiver with input a ' connected to a, input b ' connected to b, and ground c ' connected via the signal return to ground c. the v.35 interface requires a t or delta network termination at the receiver end and the generator end. the receiver differen- tial impedance measured at the connector must be 100 w 10 w , and the impedance between shorted termi- nals (a ' and b ' ) and ground (c ') must be 150 w 15 w . in v.35 mode, both switches s1 and s2 inside the LTC1546 are on, connecting a t network impedance as shown in figure 27. the 30k input impedance of the receiver is placed in parallel with the t network termination, but does not affect the overall input impedance significantly. the generator differential impedance must be 50 w to 150 w and the impedance between shorted terminals (a and b) and ground (c) must be 150 w 15 w . no-cable mode the no-cable mode (m0 = m1 = m2 = 1) is intended for the case when the cable is disconnected from the con- nector. the charge pump, bias circuitry, drivers and receivers are turned off, the driver outputs are forced into a high impedance state, and the supply current drops to less than 200 m a. note that the LTC1546s r2 and r3 receivers continue to be terminated by a 103 w differen- tial impedance. charge pump the LTC1546 uses an internal capacitive charge pump to generate v dd and v ee as shown in figure 28. a voltage doubler generates about 8v on v dd and a voltage inverter generates about C 7.5v on v ee . four 1 m f surface mounted tantalum or ceramic capacitors are required for c1, c2, c3 and c4. the v ee capacitor c5 should be a minimum of 3.3 m f. all capacitors are 16v and should be placed as close as possible to the LTC1546 to reduce emi. figure 28. charge pump figure 27. v.35 receiver configuration figure 26. typical v.35 interface a a ' b c b ' c ' generator balanced interconnecting cable load cable termination receiver 1546 f26 50 w 125 w 50 w 50 w 125 w 50 w r3 124 w r5 20k LTC1546 receiver 1546 f27 a ' b ' c ' r1 51.5 w r8 6k s2 s3 r2 51.5 w r6 10k r7 10k gnd r4 20k s1 28 27 26 25 1546 f28 3 2 1 4 c3 1 f c4 1 f 5v c1 1 f c2 1 m f c5 3.3 m f LTC1546 v dd c1 + c1 v cc c2 + c2 v ee gnd + receiver fail-safe all LTC1546/ltc1544 receivers feature fail-safe opera- tion in all modes. if the receiver inputs are left floating or are shorted together by a termination resistor, the receiver output will always be forced to a logic high. dte vs dce operation the dce/dte pin acts as an enable for driver 3/receiver 1 in the LTC1546, and driver 3/receiver 1 and driver 4/ receiver 4 in the ltc1544. the invert pin in the ltc1544 allows the driver 4/receiver 4 enable to be high or low true polarity. applicatio s i for atio wu uu
14 LTC1546 the LTC1546/ltc1544 can be configured for either dte or dce operation in one of two ways: a dedicated dte or dce port with a connector of appropriate gender or a port with one connector that can be configured for dte or dce operation by rerouting the signals to the LTC1546/ltc1544 using a dedicated dte cable or dedicated dce cable. a dedicated dte port using a db-25 male connector is shown in figure 29. the interface mode is selected by logic outputs from the controller or from jumpers to either v cc or gnd on the mode select pins. a dedicated dce port using a db-25 female connector is shown in figure 30. a port with one db-25 connector, that can be configured for either dte or dce operation is shown in figure 31. the configuration requires separate cables for proper signal routing in dte or dce operation. for example, in dte mode, the txd signal is routed to pins 2 and 14 via the LTC1546s driver 1. in dce mode, driver 1 now routes the rxd signal to pins 2 and 14. multiprotocol interface with rl, ll, tm and a db-25 connector if the rl, ll and tm signals are implemented, there are not enough drivers and receivers available in the LTC1546/ ltc1544. in figure 32, the required control signals are handled by the ltc1545. the ltc1545 has an additional single-ended driver/receiver pair that can handle two more optional control signals such as tm and rl. cable-selectable multiprotocol interface a cable-selectable multiprotocol dte/dce interface is shown in figure 33. the select lines m0, m1 and dce/dte are brought out to the connector. the mode is selected by the cable by wiring m0 (connector pin 18) and m1 (con- nector pin 21) and dce/dte (connector pin 25) to ground (connector pin 7) or letting them float. if m0, m1 or dce/ dte is floating, internal pull-up current sources will pull the signals to v cc . the select bit m2 is hard wired to v cc . when the cable is pulled out, the interface will go into the no-cable mode. compliance testing the LTC1546/ltc1544 chipset has been tested by tuv telecom services inc. and passed the net1, net2 and tbr2 requirements. copies of the test reports are avail- able from ltc or tuv telecom services. the titles of the reports are: net1 and net2: test report no. net2/091301/99. tbr2: test report no. crt2/091301/99. the address of tuv telecom services inc. is: tuv telecom services inc. type approval division 1775 old highway 8, ste 107 st. paul, mn 55112 usa tel: +1 (612) 639-0775 fax: +1 (612) 639-0873 applicatio s i for atio wu uu
15 LTC1546 figure 29. controller-selectable multiprotocol dte port with db-25 connector d2 d1 ltc1544 rts dtr dsr dcd cts d3 r2 r1 r4 r3 LTC1546 ll txd scte txc rxc rxd m0 m1 m2 dce/dte v cc v dd v cc v ee gnd 2 14 24 11 15 12 17 9 3 1 4 19 20 8 23 10 6 22 5 13 18 7 16 1546 f29 c2 1 f c1 1 f c5 1 f c3 1 f c4 3.3 f scte b rts a (105) rts b dtr a (108) dtr b cts a (106) cts b ll a (141) sg shield db-25 male connector dcd a (109) dcd b dsr a (107) dsr b d4 v cc 5v charge pump + 28 3 1 2 4 5 6 7 8 9 10 11 12 13 14 1 2 3 4 5 6 7 8 10 9 invert 15 16 17 18 19 20 21 22 23 24 25 nc 27 26 25 24 23 22 21 20 19 18 17 16 15 26 27 28 c11 1 f c10 1 f c9 1 f m0 m1 m2 dce/dte m0 m1 m2 11 12 13 14 d1 d2 d3 r1 r2 r3 txd a (103) txd b txc a (114) rxc a (115) rxd a (104) txc b rxc b rxd b scte a (113) t t t t t typical applicatio s u
16 LTC1546 figure 30. controller-selectable dce port with db-25 connector d2 d1 ltc1544 cts nc dsr dtr dcd rts d3 r2 r1 r4 r3 LTC1546 ll rxd rxc txc scte txd m0 m1 m2 dce/dte v cc v dd v cc v ee gnd 3 16 17 9 15 12 24 11 2 1 5 13 6 8 22 10 20 23 4 19 18 7 14 1546 f30 c2 1 f c1 1 f c5 1 f c3 1 f c4 3.3 f rxc b cts a (106) cts b dsr a (107) dsr b rts a (105) rts b ll a (141) sgnd (102) shield (101) db-25 female connector dcd a (109) dcd b dtr a (108) dtr b d4 v cc 5v charge pump + 28 3 1 2 4 5 6 7 8 9 10 11 12 13 14 1 2 3 4 5 6 7 8 10 9 invert nc 15 16 17 18 19 20 21 22 23 24 25 nc 27 26 25 24 23 22 21 20 19 18 17 16 15 26 27 28 c11 1 f c10 1 f c9 1 f m0 m1 m2 dce/dte m0 m1 m2 11 12 13 14 d1 t t t t t d2 d3 r1 r2 r3 rxd a (104) rxd b txc a (114) scte a (113) txd a (103) txc b scte b txd b rxc a (115) typical applicatio s u
17 LTC1546 figure 31. controller-selectable multiprotocol dte/dce port with db-25 connector d2 d1 ltc1544 d3 r2 r1 r4 r3 LTC1546 dte_txd/dce_rxd dte_scte/dce_rxc dte_txc/dce_txc dte_rxc/dce_scte dte_rxd/dce_txd dte_rts/dce_cts dte_dtr/dce_dsr dte_dcd/dce_dcd dte_dsr/dce_dtr dte_cts/dce_rts dte_ll/dce_ll m0 m1 m2 dce/dte v cc v dd v cc v ee gnd 2 14 24 11 15 12 17 9 3 1 4 19 20 8 23 10 6 22 5 13 18 7 16 1546 f31 c2 1 f c1 1 f c5 1 f c3 1 f c4 3.3 f scte b rts a rts b dtr a dtr b cts a cts b dsr a dsr b cts a cts b ll a sg shield db-25 connector dcd a dcd b dsr a dsr b rts a rts b ll a dcd a dcd b dtr a dtr b d4 v cc 5v charge pump + 28 3 1 2 4 5 6 7 8 9 10 11 12 13 14 1 2 3 4 5 6 7 8 10 9 invert 15 16 17 18 19 20 21 22 23 24 25 nc 27 26 25 24 23 22 21 20 19 18 17 16 15 26 27 28 c11 1 f c10 1 f c9 1 f m0 m1 m2 dce/dte 11 12 13 14 m0 m1 m2 dce/dte d1 t t t t t d2 d3 r1 r2 r3 txd a txd b txc a rxc a rxd a txc b rxc b rxd b txc a scte a txd a txc b scte b txd b scte a rxc b rxd a dte dce rxd b rxc a typical applicatio s u
18 LTC1546 figure 32. controller-selectable multiprotocol dte/dce port with rl, ll, tm and db-25 connector 10 17 18 d2 d1 ltc1545 d3 r2 r1 r3 v cc v dd v ee gnd d4 1,19 2,20 3 4 5 6 7 8 9 r4en d4enb 15 16 nc 24 23 22 25 26 27 28 29 30 31 32 33 34 35 36 m0 m1 m2 dce/dte m0 m1 m2 dce/dte 11 12 13 14 d5 21 r4 r5 18 * *optional 21 25 ll ll rl rl tm tm ri ri LTC1546 dte_txd/dce_rxd dte_txc/dce_txc dte_rxc/dce_scte dte_rxd/dce_txd dte_rts/dce_cts dte_dtr/dce_dsr dte_dcd/dce_dcd dte_dsr/dce_dtr dte_cts/dce_rts dte_ll/dce_ri dte_ri/dce_ll dte_tm/dce_rl dte_rl/dce_tm dte_scte/dce_rxc m0 m1 m2 dce/dte v cc 5v 2 14 24 11 15 12 17 9 3 1 4 19 20 8 23 10 6 22 5 13 7 16 1546 f32 c2 1 f c1 1 f c5 1 f c3 1 f c4 3.3 f txd a txd b scte a scte b rxd a rxd b rxc a rxc b rxc a rxc b rxd a rxd b rts a rts b dtr a dtr b cts a cts b dsr a dsr b cts a cts b sg shield db-25 connector txc a txc b scte a scte b txd a txd b txc a txc b dcd a dcd b dsr a dsr b rts a rts b dcd a dcd b dtr a dtr b v cc 5v charge pump + 28 3 1 2 4 5 6 7 8 9 10 11 12 13 14 27 26 25 24 23 22 21 20 19 18 17 16 15 dte dce c11 1 f c10 1 f c9 1 f t t t t t d1 d2 d3 r1 r2 r3 typical applicatio s u
19 LTC1546 figure 33. cable-selectable multiprotocol dte/dce port with db-25 connector d2 d1 ltc1544 d3 r2 r1 r4 r3 LTC1546 dte_txd/dce_rxd dte_txc/dce_txc dte_rxc/dce_scte dte_rxd/dce_txd nc dte_rts/dce_cts dte_dtr/dce_dsr dte_dcd/dce_dcd dte_dsr/dce_dtr dte_cts/dce_rts dte_scte/dce_rxc m0 m1 m2 dce/dte v cc v dd v cc v ee gnd 2 14 24 11 15 12 17 9 3 1 25 21 18 4 19 20 8 23 10 6 22 5 13 7 16 1546 f33 c2 1 f c1 1 f c5 1 f c3 1 f c4 3.3 f rxd a rxd b rxc a rxc b rxc a rxc b rxd a rxd b rts a rts b dtr a dtr b cts a cts b dsr a dsr b cts a cts b sg shield dce/dte m1 m0 db-25 connector txc a txc b scte a scte b txd a txd b txc a txc b dcd a dcd b dsr a dsr b rts a rts b dcd a dcd b dtr a dtr b d4 v cc 5v + 28 3 1 2 4 11 12 13 14 1 2 3 4 5 6 7 8 9 nc 10 invert 15 17 16 18 19 20 21 22 23 24 25 nc 27 26 25 26 27 28 m0 m1 m2 dce/dte 11 12 13 14 dte dce mode v.35 rs449, v.36 rs232 pin 18 pin 7 nc pin 7 pin 21 pin 7 pin 7 nc cable wiring for mode selection mode pin 25 dte pin 7 dce nc cable wiring for dte/dce selection c11 1 f c10 1 f c9 1 f charge pump 5 6 7 8 9 10 24 23 22 21 20 19 18 17 16 15 d1 t t t t t d2 d3 r1 r2 r3 txd a txd b scte a scte b typical applicatio s u information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
20 LTC1546 1546f lt/lcg 1200 4k ? printed in usa dimensions in inches (millimeters) unless otherwise noted. ? linear technology corporation 1999 g package 28-lead plastic ssop (0.209) (ltc dwg # 05-08-1640) related parts part number description comments ltc1321 dual rs232/rs485 transceiver two rs232 driver/receiver pairs or two rs485 driver/receiver pairs ltc1334 single 5v rs232/rs485 multiprotocol transceiver two rs232 driver/receiver or four rs232 driver/receiver pairs ltc1343 software-selectable multiprotocol transceiver 4-driver/4-receiver for data and clock signals ltc1344a software-selectable cable terminator perfect for terminating the ltc1543 (not needed with LTC1546) ltc1345 single supply v.35 transceiver 3-driver/3-receiver for data and clock signals ltc1346a dual supply v.35 transceiver 3-driver/3-receiver for data and clock signals ltc1543 software-selectable multiprotocol transceiver terminated with ltc1344a for data and clock signals, companion to ltc1544 or ltc1545 for control signals ltc1544 software-selectable multiprotocol transceiver companion to LTC1546 or ltc1543 for control signals including ll ltc1545 software-selectable multiprotocol transceiver 5-driver/5-receiver companion to LTC1546 or ltc1543 for control signals including ll, tm and rl linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear-tech.com g28 ssop 1098 0.13 ?0.22 (0.005 ?0.009) 0 ?8 0.55 ?0.95 (0.022 ?0.037) 5.20 ?5.38** (0.205 ?0.212) 7.65 ?7.90 (0.301 ?0.311) 1234 5 6 7 8 9 10 11 12 14 13 10.07 ?10.33* (0.397 ?0.407) 25 26 22 21 20 19 18 17 16 15 23 24 27 28 1.73 ?1.99 (0.068 ?0.078) 0.05 ?0.21 (0.002 ?0.008) 0.65 (0.0256) bsc 0.25 ?0.38 (0.010 ?0.015) note: dimensions are in millimeters dimensions do not include mold flash. mold flash shall not exceed 0.152mm (0.006") per side dimensions do not include interlead flash. interlead flash shall not exceed 0.254mm (0.010") per side * ** u package descriptio

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